Particularly in view of volatility of random access memory chips as conventionally used in modem computer systems, in recent years, great effort has been made to bring non-volatile MRAM cells into practical use enabling the manufacture of instant-on systems that come to life as soon as the computer system is turned on. An MRAM cell basically includes a stacked structure of at least two magnetic layers that are separated by a non-magnetic tunneling barrier layer to form a magnetoresistive tunnel junction element or a conductive layer to form a magnetoresistive conductive junction element, both of which are commonly referred to as magnetoresistive junction elements. Contrary to conventional DRAMs, digital information is not maintained by power but by differently oriented magnetizations in the magnetic layers. More specifically, in an MRAM cell, magnetization of one magnetic layer is fixed or pinned, while magnetization of the other magnetic layer is free to be switched between two preferred directions along an easy axis of magnetization thereof, which typically is chosen to be in parallel alignment with the fixed magnetization. One bit of information thus is stored using the two different orientations of the freely switchable magnetization with respect to the fixed magnetization.
In the well-known standard CMOS process for manufacturing of MRAMs, upon a silicon or other suitable semiconductor substrate provided with active devices such as transistors and the like, metal lines and via contacts are used to provide interconnections for the integrated circuit and the magnetoresistive memory cell array. These interconnections typically are formed by depositing a dielectric layer above the semiconductor substrate, masking and etching thereof, followed by a metal deposition and planarization of the metal, all in a well-known manner. In accordance with the standard CMOS process nomenclature, metallic lines forming the first layer of interconnects are referred to as the first metallization layer (M1) and via contacts formed in a layer of dielectric material deposited above the first metallization layer M1 are referred to as the first via layer (V1). Likewise, metal lines formed in a layer of dielectric material deposited above the first via layer are referred to as the second metallization layer (M2), followed in sequence by a second via layer (V2) formed thereupon, a third metallization layer (M3) formed thereupon, and so on to provide as many via layers and metallization layers as are needed for the specific apparatus and application.
Reference is now made to FIG. 4 depicting a partial vertical sectional view of an intermediate product in a typical conventional process of manufacturing an MRAM cell. A substrate 1 is provided, which has above a surface of a semiconductor substrate provided with active structures, which is not shown in FIG. 4, a layer of dielectric material formed which is provided with metallic lines 2 for instance made of copper (Cu) to thereby create a metallization layer 3, which may for instance be identified as second metallization layer (M2). On the metallization layer 3, a dielectric layer 17 for instance made of silicon nitride (SiN) typically is formed which is provided with a via contact 4 for electrically connecting metal line 2 with a conductive plate 14 that is in electric contact with magnetoresistive junction element 5 formed above the dielectric layer 17. The magnetoresistive junction element 5 is embedded in a dielectric layer 6 for instance made of silicon oxide, onto which a SiN-layer 7 is formed to enhance deposition of an interlayer dielectric 8 for instance made of silicon oxide.
FIG. 4 shows a situation where a first opening 9 has already been etched which opening then is to be filled with conductive material for electrically contacting the magnetoresistive junction element 5 from above. Likewise, second opening 10 in the chip periphery has been etched, which is to be filled with conductive material to electrically connect metal line 2 with another metal line being part of another metallization layer (e.g., third metallization layer (M3)) formed thereupon (not shown in FIG. 4). Etching of the opening 10 typically is a two- or three-step process, i.e., a first etch step of etching opening 9 and simultaneously partly etching opening 10 down to the height of protrusion 11, and after creating an appropriate mask that is opened at partly etched opening 10, a second etch step in the peripheral region of the chip only to etch opening 10 down to the SiN-layer 17 and a third etch stop to etch opening 10 down to metal line 2, where the second and third etch steps relating to the second opening 10 may also be combined into a single etch step.
In such conventional manufacturing of MRAM cells as explained referring to FIG. 4, a problem arises that, as the magnetoresistive junction element 5 as shown in FIG. 4 is formed from a corresponding stack of layers deposited on the SiN-layer 17 beforehand using conventional etch techniques, resputtering effects are very likely to occur that may lead to the undesired deposition of polymeric/metallic compositions on side wall regions 12 of the formed magnetoresistive junction element 5. Otherwise, etching of the second opening 10 down to metal line 2 due to over-etching thereof may also create polymeric/metallic compositions that are particularly deposited in a bottom region 13 of the opened metal line 2 and on a top surface of the magnetoresistive junction element 5.
Such polymeric/metallic residuals, however, may be embedded in later process steps and can cause severe problems as to an outgassing thereof or modification or creation of interface layers. Accordingly, in order to avoid such problems, removal of the polymeric/metallic residuals has been envisaged using a dedicated cleaning step as usual after having created openings 9, 10 for instance using water diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid. However, as has been experienced, such conventional cleaning step cannot be done, since polymeric/metallic residuals on the side walls of the magnetoresistive junction element 5 are etched-off to thereby create small trenches at the side walls of the magnetoresistive junction element 5 which are filled with conductive material in filling the opening 9 with conductive material, so that conductive paths (shorts) in the magnetoresistive junction element 5 bridging the magnetic layers can be formed. Otherwise, removal of the polymeric/metallic residuals on a bottom area of the second opening 10 may risk damage or at least degradation of the electrical properties of the opened metal line.